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Silterra/CEDEC Track
   This competition track is formed out of collaboration of two parties, where
   Silterra provides Silterra IC process technologies
   CEDEC provides EDA tool access and support



 

Silterra’s CMOS Logic technologies provide optimal combination of performance in term of power, speed and gate density, to meet the stringent product requirement in Consumer, Communication and Computing applications. The Low Power / High Vt CMOS Logic technologies is customized for digital processors used in portable consumer applications.

SilTerra’s 180nm, 160nm and 130nm Mixed-Signal and RFCMOS technologies are built from the proven CMOS Logic platform with additional active and passive RF/analog components. These RF/analog components features high precision MiM ( Metal-Insulator-Metal), Finger Capacitor, Varactor, Diode, Thick Metal Inductors, Deep Nwell, Multi-Vt and High precision resistors which are characterized up to 20GHz range. These technologies are well suited for RF/analog applications used in WLAN, Bluetooth, RFID, Zigbee applications.

 

Further, Silterra is expanding into more-than-Moore technologies such as MEMS (Micro Electro Mechanical Systems) including RF MEMS, bio-MEMS, high-power technologies such as BCD, silicon compatible surface and bulk acoustic wave devices, photonics, optical MEMS, etc. The competition participants are thus also free to explore ‘More-than-Moore’ technologies for their design competition projects. The areas need not necessarily be limited to those mentioned above. We encourage the participants to compete in these emerging research areas with a focus on modeling, design, fabrication and materials aspects.
 
Competition participants can choose to use one of the following technologies: CMOS Logic CL180G, CMOS Logic CL130G, CMOS Mixed Signal / RF CL180MR, or CMOS Mixed Signal / RF CL130MR.


Listed below are some of the design ideas for reference. Applicants may propose projects along these ideas or any other VLSI design topics using one of the Silterra process technologies.
ESD protected I/O libraries
Development of standard cells libraries
Design of circuit blocks for RF applications
Development of model extraction algorithms
Development of testing and validating methodologies for characterizing the substrate coupling noise in mixed-signal circuits.


Below is a list of tools Silterra process technologies supported.



SilTerra’s CL180G (0.18 µm CMOS Logic Generic) baseline technology is process matched to foundry standard and positioned for main-stream digital consumer & communication related applications. The technology offers the best combination of density, speed and power which are supported by a complete set of silicon proven standard design libraries, SRAM compiler, I/O and IP’s.
CL180G Key Process Features
 
Single-poly and up to six metal layers
Dual gate: 1.8V core and 3.3V I/O
Cobalt silicided source, drain and gate
Shallow trench isolation
Aluminum metallization with tungsten plug
FSG inter-metal dielectric
Metal-Insulator-Metal (MIM) Capacitor (Option)
SRAM bit cell: 4.65 µm²
   

Physical Design Rule

 
   

Electrical Design Rule (Specification)

 

SilTerra’s CL130G technology (0.13µm CMOS Logic Generic) is a all-copper process features borderless contacts and vias and up to eight layers of metal. This technology offers high speed and high gate density performance which is suitable for design in high speed digital consumer, wired communication and computation related applications.
CL130G Key Process Features
 
Multiple voltages: 1.2V core, 2.5V/3.3V I/O
Single-poly, up to eight metal layers
SG inter-metal dielectric
High Vt option available
Dual damascene copper metalization
RO delay: 20ps/stage (Nominal Vt)
Gate density: 230 KG/mm²
SRAM cell: 2.43 µm² and 2.14µm²
   

Physical Design Rule

 
   

Electrical Design Rule (Specification)

 

Silterra’s CL180MR (0.18 µm RFCMOS) is developed specifically for wireless applications in WLAN a/b/g, Bluetooth, RF transceiver, & tuner. Many RF circuits and models already proven in our RFCMOS technology. This technology is supported a complete RF models and RF design kits with silicon proven.
CL180MR Key Process Features
 
Single-poly and up to six metal layers
Supports 1.8V and 3.3V power supplies
Shallow trench isolation
Dual gate oxide
Surface channel NMOS and PMOS
Cobalt silicided source, drain and gate
Borderless contact and vias
High density plasma gap fill
FSG inter-metal dielectric
Native transistors
Metal-Insulator-Metal Capacitor (1 fF/µm² or 2 fF/µm² )
Thick metal spiral inductor
Varactor Metal Finger Capacitor (1.30 fF/µm²)
Thick Metal Spiral Inductor (2.3 µm)
Ft NMOS (56.2 GHz)
   

Physical Design Rule

 
   

Electrical Design Rule (Specification)

 

Silterra’s CL130MR (0.13um RFCMOS) is developed specifically for wireless applications in WLAN a/b/g, Bluetooth, RF transceiver & tuner. Many RF circuits are already proven in the RFCMOS technology. This technology is supported with complete RF models and RF design kits that are silicon proven.
CL130MR Key Process Features
 
Single-poly and up to six metal layers
Supports 1.8V and 3.3V power supplies
Shallow trench isolation
Dual gate oxide
Surface channel NMOS and PMOS
Cobalt silicided source, drain and gate
Borderless contact and vias
High density plasma gap fill
FSG inter-metal dielectric
Native transistors
Metal-Insulator-Metal Capacitor (1 fF/µm² or 2 fF/µm² )
Thick metal spiral inductor
Varactor Metal Finger Capacitor (1.30 fF/µm²)
Thick Metal Spiral Inductor (2.3 µm)
Ft NMOS (56.2 GHz)
   

CL130MR Device Performance

 
 

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