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Silterra/CEDEC Track
 
 

Resources for EDA Tools

CEDEC will provide access to EDA tools to support the integrated circuit (IC) design flow from front-end design entry to back-end design verification. Three separate sets of EDA tools will be provided, depending on need basis, as listed below:

Digital Design EDA Tools (Synopsys)
Stages
Tool
Front End
1. RTL coding / logic simulation
Synopsys VCS
2. Logic synthesis
Synopsys Design-Compiler
3. Gate logic simulation
Synopsys VCS
Back End
4. Static timing analysis
Synopsys PrimeTime
5. Floorplan, clock tree synthesis, power analysis, place & route
Synopsys Astro
6. Physical verification
Synopsys Hercules
7. Physical extraction
Synopsys Star-RCXT
8. Final static timing analysis
Synopsys PrimeTime
9. Final post layout simulation
Synopsys VCS

Custom IC Design EDA Tools (Mentor Graphics)
Stages
Tool
Front End
1. Schematic entry
Mentor Graphics Design Architect
    Standard cell library
CEDEC Standard Cell Library

Silterra 0.18 um process

Compatible with Mentor Graphics
Include 84 cells:


combinational cells

sequential cells
other complex cells
2. Circuit simulation Mentor Graphics Eldo Analog Simulator
Mentor Graphics Eldonet / Eldo RF
Mentor Graphics Xelga
Back End
3. Layout
Mentor Graphics IC Station
4. Physical verification
Mentor Graphics Calibre DRC, Calibre LVS
5. Physical extraction
Mentor Graphics Calibre xRC

Analog Design EDA Tools
Stages
Tool
Front End
1. Schematic entry
Cadence Analog Design Environment
Cadence Virtuoso Schematic Editor
2. Circuit simulation
Cadence Virtuoso Spectre Circuit Simulator
Cadence Virtuoso Spectre RF Simulation Option
Back End
3.Layout drawing
Cadence Virtuoso XL Layout Editor
4. Physical verification
Mentor Graphics Calibre DRC, Calibre LVS
5. Physical extraction
Mentor Graphics Calibre xRC

CEDEC EDA Tool Technical Support
E-mail
eda_support@cedec.usm.my
Phone
+604-599 5817 (Mr Wan Mohd Hafizi Bin Wan Hassin or Mdm Nuha Binti A. Rhaffor)
Contact hours: Monday to Friday, 9am - 5pm



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