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Silterra/CEDEC/Altera
Track
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| Resources
for EDA Tools |

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CEDEC will provide access to EDA
tools to support the integrated
circuit (IC) design flow from
front-end design entry to back-end
design verification. Three separate
sets of EDA tools will be provided,
depending on need basis, as listed
below:
Digital
Design EDA Tools (Synopsys)
Stages
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Tool
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Front End
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1. RTL coding / logic
simulation
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Synopsys VCS
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2.
Logic synthesis
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Synopsys
Design-Compiler
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3. Gate logic
simulation
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Synopsys VCS
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Back End
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4.
Static timing analysis
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Synopsys
PrimeTime
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5. Floorplan, clock
tree synthesis, power
analysis, place & route
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Synopsys Astro
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6.
Physical verification
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Synopsys
Hercules
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7. Physical extraction
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Synopsys Star-RCXT
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8.
Final static timing analysis
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Synopsys
PrimeTime
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9. Final post layout
simulation
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Synopsys VCS
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Custom
IC Design EDA Tools (Mentor
Graphics)
Stages
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Tool
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Front End
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1. Schematic entry
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Mentor Graphics Design
Architect
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Standard cell library
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CEDEC
Standard Cell Library
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| 2. Circuit simulation |
Mentor Graphics Eldo
Analog Simulator
Mentor Graphics Eldonet /
Eldo RF
Mentor Graphics Xelga
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Back End
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3.
Layout
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Mentor
Graphics IC Station
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4. Physical
verification
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Mentor Graphics
Calibre DRC, Calibre LVS |
5.
Physical extraction
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Mentor
Graphics Calibre xRC |
Analog
Design EDA Tools
Stages
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Tool
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Front End
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1. Schematic entry
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Cadence Analog Design
Environment
Cadence Virtuoso Schematic
Editor
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2.
Circuit simulation
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Cadence
Virtuoso Spectre Circuit
Simulator
Cadence Virtuoso Spectre RF
Simulation Option
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Back End
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3.Layout drawing
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Cadence Virtuoso XL
Layout Editor
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4.
Physical verification
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Mentor
Graphics Calibre DRC,
Calibre LVS
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5. Physical extraction
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Mentor Graphics
Calibre xRC
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CEDEC
EDA Tool Technical Support
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