IC Design Track

This competition track invites any project on integrated circuit (IC) design. IC design comprises of the following design phases where students will get opportunity to expose to industry delicate design flow to design a good quality silicon product.

Architectural Specifications: This stage mainly defines the required functionality of the products which customers are looking for namely its functions (SIP-Soft IP, HIP – Hard IP, Analogue), speed/frequency, power consumption, size/area and what specific technology will be used to implement the design.
Micro-Architectural (uArch) Design: Hardware description of the design (industrial terms RTL – Register Transfer Level) will be created based on the Architecture specifications. RTL language such as System Verilog, will be coded and simulated in pre-Silicon design environment with the help of EDA tools to ensure the functionality of the design is validated in accordance with architectural specifications.
Logic/Circuit Design: RTL language will be converted to a gate-level netlist through a process known as logic synthesis. This process is performed by industrial EDA synthesis tool which takes in standard cell libraries, design constraints and RTL codes to generate the gate level netlist. The gate-level netlist basically depicts circuit information in the form of technology logic gates and connections between them. EDA synthesis tool will need directed constraints to generate a gate level netlist to achieve the design timing, power and area specifications. Design For Testability (DFT) insertion process is also carried in this stage.
Physical Design: All the synthesized gate level netlist will be translated into a physical geometric layout representation in silicon wafer. This process will leverage the industrial Automatic Place and Route (APR) tool to achieve its goal. It will first involve “chip floor-planning ” of the design functions namely defining the location of design blocks or cells aligning to the operating voltage domain as well as the location of the primary input/output interfaces of the design. The placement of the physical cells in each design block which includes Analogue or external IP blocks will then be performed. Clock Tree Synthesis (CTS) will also be carried out in this stage before the design are fully placed and routed.
Sign-off: Once the design is fully routed, it will need to go through a series of physical design verification processes before it can be signed off for fabrication. All the physical effects related to manufacturing process technology will need to be modelled accurately during the signoff verification run. Physical effects such as capacitive & resistance of the wires, signal integrity/crosstalk, technology process variations, and foundry layout design rules are some of the critical sign-off items which must be modelled, extracted and verified before fabrication.
Fabrication: Final verified GDSII (GSD2) file from physical design phase will be channelled to foundry to fabricate into the silicon wafer.

IC design track will require participants to design a hardware and implementing it with silicon design flow. The participants can leverage the Front-End (FE) and Back-End (BE) design flow environment with industrial EDA tools provided by university. The goal is for participants to showcase their design work on how to enable a low-power and high-quality silicon by emulating the silicon design with Intel FPGA.

Design & Implementation:

RTL language: Verilog
Design tool: Synopsis VLSI design toolset
Prototype: Intel FPGA development kit

Sample topics:

Smart VLSI AI design system to detect illegal car or intruders at company or university campus without valid pass.
Smart VLSI AI design system to detect the availability of parking space at company or university campus
VLSI Speech recognition design system using Digital Signal Processing (DSP) techniques to recognize 4 basic command words: UP, DOWN, LEFT, RIGHT where implementation can be extensible to other words.
VLSI design and implementation of a hardware-based image tile compression engine using Run-Length Encoding (RLE) algorithm supporting up to 127 colors.

Benefits of joining:

Micro-credential training on Verilog design, FPGA prototyping, and IC design flow.
Industrial exposure on the standard cells design as used in VLSI design flow.
Hands-on experience on updated industrial EDA tools as adopted by many leading industrial companies.
Enhance Industrial knowledge on the updated VLSI design flow and technology from Intel.
Personal coaching provided by technical buddy from Intel.
Enhance your employability and access to high-income job opportunities.

Stages		Tool
Front End	1. RTL coding / logic simulation	Synopsys VCS
	2. Logic synthesis	Synopsys Fusion Compiler
	3. Gate logic simulation	Synopsys VCS
Back End	4. Static timing analysis	Synopsys PrimeTime
	5. Floorplan, clock tree synthesis, power analysis, place & route	Synopsys Fusion Compiler
	6. Physical verification	Synopsys Hercules
	7. Physical extraction	Synopsys Star-RCXT
	8. Final static timing analysis	Synopsys PrimeTime
	9. Final post layout simulation	Synopsys VCS

IC Design Track

IC Design Track

Resources for EDA Tools

IC Design EDA Tools (Synopsys)